In the field of digital systems design, considerable efforts have been directed towards shortening product-development cycles. One of the significant factors in the length of such product development cycles is the time required for the design and fabrication of digital integrated circuits (IC's). Once a circuit design is completed, it generally takes at least four weeks, and often several months, to fabricate a silicon version of the circuit in a "chip." To reduce the design and fabrication interval, attempts have been made to provide various types of user-definable, or programmable, logic devices (PLD's). Prior PLD's include, inter alia, programmed logic arrays (PLA's) and gate arrays.
In the field of programmable logic, there are generally four strata of integrated-circuit customization available: (1) full custom IC's; (2) standard cell-based IC's; (3) mass-programmable IC's, such as gate arrays; and (4) user-programmable IC's, such as programmable logic devices. The first two alternatives involve customization of all mask layers required to manufacture the IC to the user's specifications and are therefore often referred to as "custom" IC design. The third alternative is sometimes called "semi-custom" IC implementation because only a few of the mask layers are customized to the users' specifications. The fourth alternative, user-programmable IC's, includes those IC's in which no customization of mask layers is required. The present invention falls into that latter category. The trade-offs between these various alternatives involve the time required to bring a new product design to market, engineering cost, expected unit volume, ease of use of design tools and familiarity with the design methodology.
Until recently, PLD's generally could be programmed only once, at the time of manufacture----they were generally not reprogrammable. Such programming has been accomplished by various methods. In PLA's, fusible-link bipolar technology has been employed, wherein such links are "blown" open to program these devices. In gate arrays, a custom metallization layer is deposited to interconnect the logic elements and provide the programming. Alternatively, a laser may be used to break connections in a metallization layer. The most significant limitation on these approaches is that the device can be programmed only once. For example, after an internal fuse has been blown, the device cannot be reprogrammed. Further, since fuses can only be blown once, bipolar PLD's can only be tested destructively. Such testing methods never allow for full evaluation, so most users of bipolar programmable logic devices have resorted to extensive post-programming testing specific to their applications. Additionally, a device which is only programmable one time (i.e., at the factory or in the field) must be discarded if a programming error is discovered or a change of program is desired.
Recently, a new genre of user-programmable IC's has been developed; these new IC's are electrically-programmable and reprogrammable logic devices, such as reprogrammable gate arrays and the device and system of my aforesaid U.S. Pat. application No. 803,536. To emphasize the reprogrammability of such components, they are sometimes called "erasable, programmable logic devices," or EPLD's. By contrast with earlier program-once technologies, an EPLD can be programmed more than once; therefore, an error in programming can be corrected by simply reprogramming the device. Another advantage of EPLD's is that they may be implemented in CMOS technology, rather than bipolar technology, since fuses are not required. This allows a substantial increase in logic density. Further, since the devices are reprogrammable, the entire device can be fully, nondestructively tested at the factory; such testing is independent of any device application and therefore need not be the user's responsibility.
In general, an EPLD comprises an array of logic elements and programmable means for interconnecting those elements. The choice of logic elements made available in the device, the interconnection mechanism and the logical and physical layout of components greatly influence the properties and capabilities of an EPLD. Consequently, EPLD's designed for one type of application may not be optimal for another type of application.
The most common earlier approaches in programmable logic devices, and a currently leading approach in EPLD's, employ variations of the PLA architecture, which is composed of an array of AND gates connected to an array of OR gates. Most PLD's add to these arrays input and output blocks containing registers, latches and feedback paths. The connections between the AND and OR arrays are programmable, as are the input and output blocks and feedback paths. Programmability of these connections is achieved through the use of fusible links, EPROM cells, EEPROM cells or static RAM cells.
Typical EPLD's are represented by the EPLD models 5C031, 5C032, 5C060, 5C090, 5C121, 5C180 and related devices of Intel Corporation, Santa Clara, Calif., described in the Intel publication titled User Defined Logic Handbook, EPLD Volume, 1986. Another good example of a programmable logic device is the Logic Cell Array (a trademark) from Xilinx, Inc. Both companies market EPLD's and associated development systems which provide tools to aid in the design of logic systems employing their respective programmable devices.
The Intel devices employ an architecture based on the "sum of products" PLA structure with a programmable AND-array feeding into a fixed OR-array. Design entry is accomplished by one of four methods: (1) schematic input of the logic circuit; (2) net list entry, by which the user enters the design by describing symbols and interconnections in words, following a standardized format; (3) state equation/diagram entry; and (4) Boolean equations. Intel's development system converts all design entry data into Boolean equations which are then converted to a sum-of-products format after logic reduction. The configurable logic block used in the Xilinx product is programmed either by the entry of Boolean equations or by the entry of a Karnaugh map.
While these EPLD architectures may represent an advance over prior logic systems which did not provide user programmability, they are far from ideal. The requirement that Karnaugh maps and Boolean equations be used to program these devices means the user must have extensive training in digital logic design. This, of course, limits the user base. Further, these approaches do not allow the designer to easily lay out circuits on a chip or see how efficiently or inefficently an arrangement of circuit modules utilizes a chip. Neither does either approach provide a tool for the modular, hierarchical design of complex circuits. Other deficiencies will be apparent to those skilled in the art.
Accordingly, it is an object of the present invention to provide a reprogrammable digital logic device which can be programmed easily to implement a large class of digital circuits.
Another object is to provide such a device which is electrically reprogrammable.
It is a further object of the invention to provide a programmable, universal digital logic cell or set of cells which can be employed to implement a large class of digital circuits.
Yet another object of the invention is to provide a computational apparatus and architecture in which concurrency can be extended to a very low level of granularity.
Another object of the invention is to provide a reprogrammable digital logic device which can be programmed and reprogrammed easily to realize a large class of Petri nets.
Another object of the invention is to provide a reprogrammable digital logic device which can be programmed and reprogrammed easily to implement self-timed logic systems.
Still another object of the invention is to provide a method, based upon graphics operations, to facilitate the programming of individual EPLD's as well as systems built up from a plurality of similar EPLD's.
A still further object of the invention is to provide a programmable logic device and a graphical programming environment therefor, which together support the modular, hierarchical construction of logic circuitry by means of block diagrams.
Yet another object of the invention is to provide a programmable logic device and a development system therefor, which support the translation, rotation and reflection of logic circuits and circuit blocks in designing a system on one or more of such devices.